The present invention relates to a buffer control apparatus applicable to a data processing system for controlling delivery of data to a store.
Generally, a main store reads or writes data at a speed which is lower than a read or write requesting speed of a processing unit and, therefore, waiting is involved in writing data into the main store in response to successive write requests. Systems elaborated to eliminate such a drawback are disclosed in U.S. Pat. No. 4,156,906 and U.K. Patent Application GB No. 2,010,547A, for example. In the disclosed systems, a processing unit is furnished with a write buffer device so that data may be written into the write buffer device and, after the write operation, a write request may be fed from the write buffer device to the main store when the main store is empty.
Although the write buffer device installed in the systems described above commonly accommodate one write command, even a buffer device capable of stacking a plurality of write commands therein causes write requests to be delivered sequentially to the main store. Therefore even when local write commands are sequentially applied for a common address region of the main store, the preceding write request is sent out from the write buffer device if any vacancy exists in the main store. It follows that if the succeeding write request shares the same address region with preceding one, the main store does not become empty until a processing for the latter is completed, giving rise to the problem of waiting. Especially, in a multi-processor system, an increase in the number of write commands proportionally increases write operations in the main store and, thereby, lowers the performance of the whole system.